Modern EV systems requires a reliable bridge between the high voltage, dangerous tractive system, and the lower voltage traditional 12V logic rail. This was a problem that UQ Racing faced for a number of years, as previous iterations had a history of catrastrophic failures during testing. The stakes for this module were exceptionally high. It serves as the primary power source for the Accumulator Indicator Light (AIL)—a safety-critical component mandated by Formula SAE rules to signal when the 600V system is active—as well as the internal management electronics within the high-voltage battery enclosure.
Recognizing that the reliability of the entire vehicle’s safety architecture depended on this single point of failure, I took the initiative to lead a complete ground-up redesign. My objective was to move beyond "patching" the legacy hardware and instead engineer a robust, simulation-validated solution that could withstand the thermal and electrical rigors of a 600V powertrain.
The previous design was based on the LT8316 flyback controller. During a controlled ramp-up to 450V, the IC experienced a thermal "blow-up" despite a low current draw (< 10mA). I conducted a deep dive into the failure mode by investigatng the thermal profiles of the chip, where I identified a critical oversight in the intial component selection:
The Error: The design used the LT8316F package, which lacks an exposed ground pad for heat dissipation.
The Evidence: By analysing an evaluation board that uses the LT8316FE (the variant with an expposed ground pad for heat dissipation), I noted that the chp only reached 47 degrees at 600V. Using the given junction to ambient and junction to case thermal resistances, I modelled the theoretical junction temperature and concluded that localised hotspots in the non heat sink variant were likely causingg internal thermal runaway at high input voltages.
Legacy LT8316 Design - Can you spot where the failure mode was?
Since the LT8316FE - the variant with a thermal ground pad - was out of stock through mainstream distributers, I performed a trade-off analysis to find a more robust solution for the FSAE environment, which eventually led me to the LNK3206GGQ by LinkSwitch. While there were other options, this was chosen as it was readily available, easily adaptable for a 600V range (most EV automotive solutions were designed for a 400V head limit), and fits within the project's budget constraint ($150).
Why the LNK3206GGQ?
Higher efficiency: Flyback design is superior to traditional diode ladder or current mirror designs in effciency
Integrated Safety: Toplogy allows for the converter to easily handle the full 600V battery potential by distributing the voltage stress across an external high voltage MOSFET as well as the controller's internal switch
Proven Reliablity: Highly recommended within online forums for buck DCDC designs, meaning more support is available in the design cycle
Whilst going through the design stages, I decided to set out a few specifications and objectives:
Voltage Regulation: The design must be able to step down an input of 60V - 600V to a stable 12V rail. Although it is primarily designed for the EV (600 V), I also wanted it to be modular enough to be used in the Autonomous EV (200 V) as well.
Ultra Low No Load Consumption: Since this circuit will be connected to the tractive system battery, I wanted to minimise the drain on the battery during idle periods, so that the actual juice can be used to make the EV go further and faster instead. I aimed to keep the board under 60 degrees as per FSAE rulesets.
Power Integrity: I targeted an output voltage ripple of below 500 mV pk-pk during standard loads due to the tolerances of the devices that this DCDC powers.
Magnetic Stability: Since the DCDC is located within the high voltage enclosure, I wanted to ensure that the board's power inductor maintains continuous conduction mode (CCM) under full load to prevent EMI spikes that might occur which could affect the delicate electronics near it.
With that in mind, these were the specific design choices I made off this:
Following the manufacturer's documentation and recommendendations, the LNK3206GQ and MOSFET Q1 are arranged in a StackFET configuration.
Startup Sequence: I used a resistor to turn the MOSFET on during initial startup. This allows the BYPASS pin capacitor to charge up from the input voltage so the controller can kick in. The resistor R5 and capacitor C5 are used to balance the voltage sharing of the MOSFET and LNK3206GQ on startup.
Voltage Protection: The Zener diodes D4, D7 and D8 provides gate current for Q1 while turning it on and off. This also limits the voltage across the LNK3206GQ to less than 600 V to protect it from any accidental voltage spikes due to renegerative braking or torque vectoring.
Oscillation Prevention: The resistor R7 is placed in series to limit the gate charging current to dampen out any potential high frequency oscillation, and the Zener diode D3 limits the gate to source voltage of Q1.
As for the output, I focused on achievingg a reliable energy transfer and ensuring that the output rail remains stable under load.
Energy Transfer: During the on time of the LNK3206GQ, the current ramps up in L1 and is simultaneously delivered to the load. When the LNK3206GQ is off, the inductor current then ramps down the free wheeling diode D5 and D6 into C4, which is also delivered to the load. The usage of two freewheeling diodes in series was implemented to meet the manufacturer's 80% diode voltage derating requirement, as ultrafst diodes with low T_RR were used due to the high power delivered through it.
Ripple Reduction: The capacitor C4 was carefully chosen to have a very low ESR to meet the targeted 100 mV output ripple. The output voltage across L1 is rectified and smoothed by D1, D2 and C2 during the off time of the LNK3206GQ.
Feedback Loop: Since the flyback controller requires a feedback loop to complete its closed loop control system, the voltage across C2 is fed through a voltage divider between R2 and R3 into the controller's feedback pin. The values of R2 and R3 are chosen such that the nominal output voltage of the feedback loop is 2V as per manufaturer's specification for better output voltage regulation and efficiency. This sees that the current going into the feedback pin is 49 µA, allowing the overall output tolerance of 5% at rated output current.
At first, it seemed that the routing for the DCDC was fairly straightforward due to the relatively low number of components used. However, I soon ran into two significant challenges that I was unfamiliar with: high voltage isolation and thermal regulation.
Here, my objective was to eliminate localised hotspots to prevent thermal runaways as seen on the LT8316 design, which was achieved through the following:
Increased Copper Weight: During the fabrication process, I increased the copper weight from the standard 1.2 oz to 2 oz for all layers. This was doen to increase the total cross sectional area of the traces and planes to signicantly reduce the I^2R losses and provide more thermal mass for heat dissipation
Polygon Pours: I used an extensive amount of copper pours around high thermal gradient components. By maximising the surface area of these planes, I was able to effectively turn the PCB itself into a passive heatsink.
Stitching Via Arrays: According to the manufacturer documentation, the power inductor L1 and freewheeling diodes D5 and D6 are the primary heat generators. I decided to implement a high density stitching via array to thermally couple polygon pours on both the top and bottom copper layers, thus allowing heat to disspate through both sides of the board.
To meet strict safety regulations, I had to ensure that the High Voltage system remained galvanically isolated from the Ground Low Voltage system of the car.
Galvanic Isolation: I controlled the output of the board through a high voltage rated reed relay. This provided physical separation between the 600V accumulator circuit and the rest of the vehicle's 12V electrical system, preventing any potential faults like shocks or shorts from leaking into the rest of the car. This also helps eliminate ground loops and common node noise from occuring
Clearance and Creepage Prevention: Since this is a 600V board, I aimed to maintain proper air and surface clearance to prevent arcing. As per IPC-2221B standards, I implemented a 4mm across the board to maintain proper spacing
Environmental and Electrical Protection: To further improve the dialetrics of the board and protect it against moisture and dust, I applied a conformal coating with a thickness of 3 mil. As per IPC-2221B, tihs coating allows for a tighter clearance, going from 12.7 mm minimum clearance to the aforementioned 4mm spacing. This allowed me to make the board more compact, which was essential for fitting it in the accumulator box
As such, the final board was as follows:
To ensure that the DCDC was reliable enough, I put the prototype board through a series of stress tests to validate my thermal and electrical design choices. This was done by using a high voltage power supply through the UQ Power Electronics Lab.
Thermal Stress Test: I used a FLIR thermal camera borrowed from UQ Instrumentation Lab to monitor the board while running at a constant 600V input. Although temperature stabilised after 5 minutes, I ran the test for an additional 30 minutes to simulate the duration of an average FSAE endurance event.
At an ambient temperature of 29 degrees, the board did not exceed 45 degrees, which was well within the design limit of 60 degrees. Additionally, it shows that the vias worked, as the areas with the biggest heat built up were implemented with the stitching vias for better heat dissipation.
One limitation of this test was that it was done in an open test bench, which is not an accurate operating environment since the board will be used in a sealed enclosure. Further testings conducted should be done in an environment indicative of the actual use case to get a more realistic result,
Output and Voltage Ripple: I used a digital oscilloscope to measure the output rail to check for switching noise. The data was then exported to Matlab for analysis. This was done with a modfied oscilloscope probe, where two capacitors were added in parallel across the probe ground and tip. This was to reduce spurious signals pickup and to also simulate the capactive load attached to the DCDC. The capactors were a 0.1 uF ceramic and 47 uF aluminium electrolytic. A test load of a resistor and LED in series was applied.
Here, the average output was about 12V, with a ripple voltage of 68 mV pk-pk, which is well under the design target of 100 mV. In the future, I would like to do more tests with different load cases and periods rather than a static test to better analyse the DCDC's impulse response and total harmonic distortions.
The redesign of the AIL from a failing legacy board to a stable StackFET converter was one of the most technical challenges I’ve tackled. It pushed me to look beyond basic circuit design and into the physics of component failure and thermal management.
What I learnt:
Forensic Engineering: By analysing the previous failed design, I leanre how to perform a deep dive failure analysis. This gave me valuable experience in using datasheets as a diagnostic tool and taught me how to redesign to address these failures rather than blindly guessing
High Voltage PCB Design: Although I have contributed on high voltage PCBs in the past, this was my first solo project meaning I had to adapt a safety first mindset. I learnt to implement different safety stanards for creepage and clearance, and how to account for galvanic isolation by using relays to ensure that proper safety protocols were followed
Thermal Engineering: To prevent thermal runaways, I learnt how to design for heat dissipation. From increasing the copper weight of the board, to implementing high density thermal via stitching, I learnt how to use the PCB itself as a heatsink for power electronics.